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specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' s products or equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment. the products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for new introduction or other application different from current conditions on the usage of automotive device, communication device, office equipment, industrial equipment etc. , please consult with us about usage conditi on (temperature, operation time etc.) prior to the intended use. if there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. 62012 sy 20120111-s00002 no.a2069-1/21 LE24CBK23MC overview the dual port eeprom series consists of two independent banks, and each bank can be controlled separately using dedicated control pins. the two banks can each be controlled separately, but share the internal power supply system. in addition, this product uses a 2-wire se rial interface, and is the optimal device for realizing substantial reductions in system cost and mounting area, as well as low power consumption. this product also incorporates a combine mode that allows the two-bank configura tion (2k bits + 2k bits) to be used as a pseudo-one-bank configuration (4k bits) by setting the cobm# pin to the low level. together with the 16-byte page write function, this enables a reduction in the number of factory write processes. this product incorporates sanyo's high performance cmos eeprom technology and realizes high-speed operation and high-level reliability. the interface of this product is compatible with the i 2 c bus protocol, making it ideal as a nonvolatile memory for small-scale parameter storage. in addition, this product also supports ddc2 tm , so it can also be used as an edid data storage memory for display equipment. functions ? capacity : 2k bits (256 8 bits) + 2k bits (256 8 bits): 4k bits in total ? bank configuration : 2-bank (2k-bit + 2k-bit) ? single supply voltage : 2.5v to 5.5v ? interface : two wire serial interface (i 2 c bus*), vesa ddc2 tm compliant** ? operating clock frequency : 400khz (max) ? low power consumption : standby: 5 a (max) : one-bank read: 0.8 ma (max.) continued on next page. ordering number: ena2069 cmos ic dual port eeprom two wire serial interface (2k+2k eeprom) * : i 2 c bus is a trademark of philips corporation. ** : ddc and edid are trademarks of video electronics standard association (vesa). * this product is licensed from silicon storage te chnology, inc. (usa), and manufactured and sold by sanyo semiconductor co., ltd.
LE24CBK23MC no.a2069-2/21 continued from preceding page. ? automatic page write mode : 16 bytes ? read mode : sequential read and random read ? erase/write cycles : 10 6 cycles ? data retention : 20 years ? default data : ffh(all address) ? high reliability : adopts sanyo?s proprietary sy mmetric memory array configuration (usp6947325) noise filters connected to scl1, sda1, scl2 and sda2 pins incorporates a feature to prohibit write operations under low voltage conditions. package dimensions unit:mm (typ) 3434 pin assignment pin descriptions pin.1 scl2 clock input bank2 pin.2 sda2 data input/output pin.3 cobm# bank/combine mode change pin.4 gnd ground pin.5 sda1 data input/output bank1 pin.6 scl1 clock input pin.7 wp# write protection pin.8 v dd power supply sanyo : sop8j(200mil) 4.9 3.9 6.0 1 8 2 0.64 0.2 0.4 1.27 (0.55) 1.75 max (1.5) 0.15 scl2 sda2 cobm# gnd v dd wp# scl1 sda1 1 2 3 4 5 6 7 8 (top view)
LE24CBK23MC no.a2069-3/21 block diagram description of operation the bank1 control signals are scl1 and sda1, and the bank2 control signals are sc l2 and sda2. the control signals for each bank can be controlled separately, regardless of the other bank?s status. this enables the product to be handled like two separate eeprom mounted in a single package, which means that the bank1 and bank2 sides can be used simultaneously for two independent systems. bank mode (2k bits + 2k bits) and combine mode (internally handled as 4k bits) can be switched using the cobm# pin. in combine mode, the bank1 control signals (scl1, sda2) are used, and both bank1 and bank2 are accessed. this enables the two-bank configuration (2k bits + 2k bits) to be used as a pseudo-one-bank configuration (4k bits), which allows access to both the bank1 and bank2 areas using a single system of control signals (scl1, sda1). data correlation is guaranteed between combine mode and bank mode, enabling operation while switching the mode, such as performing write in combine mode and read in bank mode. condition detector serial controller address generator x decoder serial-parallel converter y decoder & sense amp eeprom array (2k-bit) high voltage generator write controller bank1 condition detector serial controller address generator x decoder serial-parallel converter y decoder & sense amp eeprom array (2k-bit) high voltage generator write controller bank2 bank controller & mode decoder input buffer input buffer i/o buffer i/o buffer input buffer scl1 scl2 sda1 sda2 cobm# wp#
LE24CBK23MC no.a2069-4/21 specifications absolute maximum ratings parameter symbol conditions ratings unit supply voltage -0.5 to +6.5 v dc input voltage -0.5 to +5.5 v over-shoot voltage below 20ns -1.0 to +6.5 v storage temperature tstg -65 to +150 c note: if an electrical stress exceeding the maximu m rating is applied, the device may be damaged. operating conditions parameter symbol conditions ratings unit operating supply voltage 2.5 to 5.5 v operating temperature -40 to +85 c dc electrical characteristics parameter symbol conditions v dd =2.5v to 5.5v unit min typ max supply current at reading (when either bank1 or bank2 is read) i cc 11 f=400khz 0.8 ma supply current at reading (when both bank1 and bank2 are read simultaneously) i cc 12 f=400khz 1.6 ma supply current at writing (when either bank1 or bank2 is write) i cc 21 f=400khz, t wc =5ms 5 ma supply current at writing (when both bank1 and bank2 are write simultaneously) i cc 22 f=400khz, t wc =5ms 8 ma standby current i sb v in =v dd or gnd 0.7 5 a input leakage current i li v in =gnd to v dd -2.0 +2.0 a output leakage current (sda) i lo v out =gnd to v dd -2.0 +2.0 a input low voltage v il v dd *0.3 v input high voltage v ih v dd *0.7 v input low voltage(wp# pin) v il _wp v dd < 4.0v v dd *0.2 v input high voltage(wp# pin) v ih _wp *1) v dd *0.7 v output low level voltage v ol i ol =0.7ma, v dd =2.5v 0.2 v i ol =3.0ma, v dd =2.5v 0.4 v i ol =3.0ma, v dd =5.5v 0.4 v i ol =6.0ma, v dd =4.5v 0.6 v *1: the actual v ih value of the wp# pin is 2.0v (v dd = 5.0v). capacitance /ta=25 c, f=100khz parameter symbol conditions min typ max unit in/output capacitance c i/o v i/o =0v (sda) 2 5 pf input capacitance c i v in =0v (other sda) 2 5 pf note: this parameter is sampled and not 100% tested.
LE24CBK23MC no.a2069-5/21 ac electric characteristics fast mode parameter symbol v dd =2.5v to 5.5v unit min typ max slave mode scl clock frequency f scls 400 khz scl clock low time t low 1200 ns scl clock high time t high 600 ns sda output delay time t aa 100 900 ns sda data output hold time t dh 100 ns start condition setup time t su.sta 600 ns start condition hold time t hd.sta 600 ns data in setup time t su.dat 100 ns data in hold time t hd.dat 0 ns stop condition setup time t su.sto 600 ns scl, sda rise time t r 300 ns scl, sda fall time t f 300 ns bus release time t buf 1200 ns noise suppression time t sp 100 ns write cycle time t wc 5 ms standard mode parameter symbol v dd =2.5v to 5.5v unit min typ max slave mode scl clock frequency f scls 100 khz scl clock low time t low 4700 ns scl clock high time t high 4000 ns sda output delay time t aa 100 3500 ns sda data output hold time t dh 100 ns start condition setup time t su.sta 4700 ns start condition hold time t hd.sta 4000 ns data in setup time t su.dat 250 ns data in hold time t hd.dat 0 ns stop condition setup time t su.sto 4000 ns scl, sda rise time t r 1000 ns scl, sda fall time t f 300 ns bus release time t buf 4700 ns noise suppression time t sp 100 ns write cycle time t wc 5 ms
LE24CBK23MC no.a2069-6/21 bus timing write timing scl sda d0 t wc write data acknowledge stop condition start condition scl sda/in sda/out t f t su.sta t hd.sta t aa t high t low t hd.dat t su.dat t dh t r t su.sto t sp t buf t sp
LE24CBK23MC no.a2069-7/21 pin functions (bank1) scl1 (serial clock input) pin the scl1 pin is the serial clock input pin used to access the bank1 area, and pro cesses signals at th e rising and falling edges of the scl1 clock signal. this pin must be pulled up by a resistor to the v dd level, and wired-ored with another open drain (or open collector) output device for use. in combine mode, the scl1 pin functions as the serial clock input pin that controls both bank1 and bank2 sda1 (serial data input/output) pin the sda1 pin is used to transfer serial data to the input/output of the bank1 side area and it consists of a signal input pin and n-channel transistor open drain output pin. like the scl1 line, the sda1 line must be pulled up by a resistor to the v dd level and wired-ored with another open drain (or open collector) output device for use. (bank2) scl2 (serial clock input) pin the scl2 pin is the serial clock input pin used to access the bank2 area, and pro cesses signals at th e rising and falling edges of the scl2 clock signal. this pin must be pulled up by a resistor to the v dd level, and wired-ored with another open drain (or open collector) output device for use. in combine mode, the scl2 pin is invalid. sda2 (serial data input/output) pin the sda2 pin is used to transfer serial data to the input/output of the bank2 side area and it consists of a signal input pin and n-channel transistor open drain output pin. like the scl2 line, the sda2 line must be pulled up by a resistor to the v dd level and wired-ored with another open drain (or open collector) output device for use. (common pin) wp# (write protection) pin when the wp# pin is at the low level, write protection is en abled, and write is prohibited to all memory areas within both bank1 and bank2. read opera tion can access all memory areas regardless of the wp# pin status. cobm# (combine mode) pin the cobm# pin is used to switch the eeprom internal operation between bank mode and combine mode. the eeprom operates in bank mode when the cobm# pin is at the high level, and in combine mode when at the low level. note that in combine mode, the scl2 and sda2 pins are handled as don?t care.
LE24CBK23MC no.a2069-8/21 functional description 1. start condition when the scl line is at the high level, the start condition is established by changing the sda line from high to low. the operation of the eeprom as a slave starts in the start condition. 2. stop condition when the scl line is at the high level, the stop condition is established by changing the sda line from low to high. when the device is set up for the read sequence, the read operation is suspended when th e stop condition is received, and the device is set to standby mode. when it is set up for the write sequence, the capture of the write data is ended when the stop condition is received, and the eeprom internal write operation is started. 3. data transfer data is transferred by changing the sd a line while the scl line is low. when the sda line is changed while the scl line is high, the resulting condition will be recognized as the start or stop condition. 4. acknowledge during data transfer, 8 bits are transf erred in succession, and then in the nint h clock cycle period the device on the system bus receiving the data sets the sda line to low, and sends the acknowledge signal indicating that the data has been received. the ackn owledge signal is not sent during an eeprom internal write operation. scl sda t su.sta t hd.sta t su.sto start condition stop condition t aa t dh 1 89 scl (eeprom input) sda (master output) sda (eeprom output) start condition acknowledge bit output scl sda t su.dat t hd.dat
LE24CBK23MC no.a2069-9/21 5. device addressing for the purposes of communication, the master device in the system generates the start condition for the slave device. communication with a particular slave device is enabled by sending along the sda bus the device address, which is 7 bits long, and the read/write command code, which is 1 bit long, immediately following the start condition. the upper four bits of the device address are called the de vice codes which, for this pr oduct, are fixed at ?1010?. the LE24CBK23MC has internal 3-bit slave addresses (bank1: sa2 and sa1, bank2: sb2 and sb1) following the device code, and the default slave addresses are set to sa0 = 0, sa1 = 0, sa2 = 0 and sb0 = 0, sb1 = 0, sb2 = 0, respectively. when the device code + slave address input from sda are compared with this product?s device code and the slave address set during mounting and are found to match them, this product sends back the acknowledge signal in the ninth clock cycle period, and performs the read or write operation in accordance with the read or write command code. when there is no match, the eeprom enters sta ndby mode. when executing a read operation immediately after switching the slave device, the random read command should be used. - the default internal slave address is set to sa2 = 0, sa1 = 0, sa0 = 0. - in bank mode (2k bits), the effective address bits are a7 to a0, and the effective slav e address bits are sa2, sa1 and sa0. - in combine mode (2k bits + 2k bits), the effective addr ess bits are a8 to a0, and th e slave address bits sa2 and sa1 are don?t care. a8 = 0: selects the bank1 area,; a8 = 1: selects the bank2 area. effective address slave address bank mode (cobm# = ?h?) a7 ? a0 sa2, sa1, sa0 combine mode (cobm# = ?l?) a8 ? a0 a8 = 0: 1 bank selection area a8 = 1: 2 bank selection area sa2, sa1 but sa2 and sa1 are don?t care - in combine mode (2k bits + 2k bits), bank2 communication is invalid. effective address slave address bank mode (cobm# = ?h?) a7 ? a0 sb2, sb1, sb0 combine mode (cobm# = ?l?) - - bank1 1 0 0 1 sa2 sa1 r/w msb lsb sa0 or a8 device code slave address device address word bank2 1 0 0 1 sb2 sb1 r/w msb lsb device code slave address device address word sb0
LE24CBK23MC no.a2069-10/21 6 internal mode the eeprom functions in bank mode when the cobm# pin is at the high level, and in combine mode when the cobm# pin is at the low level. 6-1. bank mode the eeprom functions in bank mode when the cobm# pin is at the high level. in bank mode, each bank (bank1, bank2) is controlled separately using dedicated control signals. the two banks are independent, and can be controlled separately regardless of the other bank?s status. this enables the eeprom to be handled as two independen t eeprom devices incorporated in a single package. in turn, this makes it possible for the bank1 and bank2 sides to be connected to the mcu of separate systems. 6-2. combine mode the eeprom functions in combine mode when the cobm# pin is at the low level. in combine mode, the bank1 control signals (scl1, sda1) are used to control both bank1 and bank2. combine mode uses the two-bank configuration (2k bits + 2k bits) as a pseudo-one-bank configuration (4k bits). in combine mode, the bank2 control signals (scl2, sda2) are handled as don?t care. in combine mode the memory area is pr ocessed as a single 4k-bit bank, so th e address msb changes from a7 to a8, and a8 becomes an effective ad dress bit. set a8 = 0 to control the bank1 area, or a8 = 1 to control the bank2 area. data correlation is guaranteed between combine mode and bank mode, enabling operation while switching the mode, such as performing write in combine mode and read in bank mode. scl1 sda1 scl2 sda2 LE24CBK23MC 00h ffh bank1 (2k-bit) 00h ffh bank2 (2k-bit) wp# scl1 sda1 scl2 sda2 LE24CBK23MC 000h 0ffh bank1 (2k-bit) 100h 1ffh bank2 (2k-bit) bank1 1 0 0 1 x x r/w msb lsb a8 wp# device code slave address device address word x:don? care
LE24CBK23MC no.a2069-11/21 7 eeprom write operation 7-1. byte writing when the eeprom receives the 7-bit device address an d write command code ?0? after the start condition, it generates an acknowledge signal. after this, if it receives the 8-bit word addr ess, generates an acknowledge signal, receives the 8-bit write data, generates an acknowledge signal and then receives the stop condition, the internal write operation of the eeprom in the designated memory ad dress will start. rewriting is completed in the t wc period after the stop condition. during an eeprom internal write oper ation, no input is accepted and no acknowledge signals are generated. 7-2. page writing this product enables pages with up to 16 bytes to be written. the basic data transfer procedure is the same as for byte writing: following the start condition, the 7-bit device addr ess and write command code ?0,? word address (n), and data (n) are input in this order while confirming acknowledge ?0? every 9 bits. the page write mode is established if, after data (n) is input, the write data (n+1) is input w ithout inputting the stop condition. after this, the write data equivalent to the largest page size can be received by a continuous process of repeatin g the receiving of the 8-bit write data and generating the acknowledge signals. at the point when the write data (n+1) has been input, the lower 4 bits (a0-a3) of the word addresses are automatically incremented to form the (n +1) address. in this way, the write data can be successively input, and the word address on the page is incremente d each time the write data is input. if th e write data exceeds 16 bytes or the last address of the page is exceeded, the word address on the page is rolled over. write data will be input into the same address two or more times, but in such cases the write data that was input last will take effect. finally, the eeprom internal write operation corresp onding to the page size for which the wr ite data is received starts from the designated memory address when the stop condition is received. sda a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 stop ack ack ack r/w w s0 / a8 s1 s2 0 1 0 1 start word address data access from master bank mode : s2, s1, s0 is effective. combine mode : a8 is effective. s2 and s1 are don? care sda a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 ack ack ack r/w w s0 / a8 s1 s2 0 1 0 1 start memory address(n) data(n) d7 d6 d1 d0 ack d7 d6 d1 d0 d7 d6 d1 d0 d7 d6 d1 d0 d7 d6 d1 d0 stop ack ack ack data(n+1) data(n+x) access from master bank mode : s2, s1, s0 is effective. combine mode : a8 is effective. s2 and s1 are don? care
LE24CBK23MC no.a2069-12/21 7-3. acknowledge polling acknowledge polling is used to find out when the eeprom internal write operation is completed. when the stop condition is received and the eeprom starts rewriting, all opera tions are prohibited, and no response can be given to the signals sent by the master device. therefore, in orde r to find out when the eeprom internal write operation is completed, the start condition, device address and write command code are sent from the master device to the eeprom (slave device), and the respon se of the slave device is detected. in other words, if the slave device does not send the acknowledge signal, it means that the internal write operation is in progress; conversely, if it does send the acknowledge signal, it means that the internal write operation has been completed. sda no ack r/w w s0 / a8 s1 s2 0 1 0 1 start w s0 / a8 s1 s2 0 1 0 1 start w s0 / a8 s1 s2 0 1 0 1 start no ack r/w ack r/w during write during write end of write access from master bank mode : s2, s1, s0 is effective. combine mode : a8 is effective. s2 and s1 are don? care
LE24CBK23MC no.a2069-13/21 8 eeprom read operations 8-1. current address reading the address equivalent to the memory address accessed last +1 is held as the internal address of the eeprom for both write* and read operations. theref ore, provided that the master device has recognized the position of the eeprom address pointer, data can be read from the memory address with the current address pointer without specifying the word address. as with writing, current address read ing involves receiving the 7-bit device address and read command code ?1? following the start condition, at which time the eeprom gene rates an acknowledge signal. after this, the 8-bit data of the (n+1) address is output serially starting with the highest bits. after the 8 bits have been output, by not sending an acknowledge signal and inputting the stop condition, the eeprom completes the read operation and is set to standby mode. if the previous read address is the last address, the address for the current address reading is rolled over to become address 0. * the current address assigned after a page write is the number of bytes written at the designated word address plus 1 if the volume of the write data is greater than 1 byte or less than or equal to 16 bytes, and is the designated word address if the volume of the write data is 16 bytes or more. if the last address of the page (a3 to a0 = 1111b) is specified as the word address for a byte write , the internal address after the write becomes the first address in that page (a3 to a0 = 0000b). 8-2. random read random read is a mode in which any memory address is sp ecified and its data read. the address is specified by a dummy write input. first, when the eeprom receives the 7-bit device address and write command code ?0? following the start condition, it generates an acknowledge signal. it then receives the 8-bit word address, and generates an acknowledge signal. through these operations, the word address is load ed into the address counter inside the eeprom. next, the start condition is input again and the current read is initiated. this causes the data of the word address that was input using the dummy write input to be output. if, after the data is output, an acknowledge signal is not sent and the stop condition is input, reading is completed, and the eeprom returns to standby mode. sda a7 a6 a5 a4 a3 a2 a1 a0 no ack ack ack r/w w s0 / a8 s1 s2 0 1 0 1 start device address word address d7 d0 stop data(n) r s0 / a8 s1 s2 0 1 0 1 start device address ack r/w dummy write current address read access from master bank mode : s2, s1, s0 is effective. combine mode : a8 is effective. s2 and s1 are don? care sda d7 d6 d5 d4 d3 d2 d1 d0 no ack ack r/w r s0 / a8 s1 s2 0 1 0 1 start device address stop access from master data(current address) bank mode : s2, s1, s0 is effective. combine mode : a8 is effective. s2 and s1 are don? care
LE24CBK23MC no.a2069-14/21 8-3. sequential read in this mode, the data is read continuously, and sequential read operations can be performed with both current address read and random read. if, after the 8-bit data has been output, acknowledge ?0? is input and reading is continued without issuing the stop condition, the address is increm ented, and the data of the next address is output. if acknowledge ?0? continues to be input after the data has been output in this way, the data is successively output while the address is incremented. when the last address is reached, it is roll ed over to address 0, and the data continues to be read. as with current address read and random read, the operation is completed by inputting the stop condition without sending an acknowledge signal. sda ack r/w r s0 / a8 s1 s2 0 1 0 1 start stop no ack device address data(n) data(n+1) d7 d6 d1 d0 d7 d6 d1 d0 ack ack d7 d6 d1 d0 data(n+x) access from master bank mode : s2, s1, s0 is effective. combine mode : a8 is effective. s2 and s1 are don? care
LE24CBK23MC no.a2069-15/21 application notes 1) software reset function software reset (start condition + 9 dummy clock cycles + st art condition), shown in the figure below, is executed in order to avoid erroneous operation after power-on and to reset while the command input sequence. during the dummy clock input period, the sda bus must be opened (set to high by a pull-up resistor). since it is possible for the ack output and read data to be output from the eeprom during the dummy clock period, forcibly entering h will result in an overcurrent flow. note that this software reset function does not work during the internal write cycle. 2) pull-up resistor of sda pin due to the demands of the i 2 c bus protocol function, the sda pin must be connected to a pull-up resistor (with a resistance from several k to several tens of k ) without fail. the appropriate value must be selected for this resistance (r pu ) on the basis of the v il and i il of the microcontroller and other devices controlling this product as well as the v ol ?i ol characteristics of the product. generally, when the resistance is too high, the operating frequency will be restricted; conversely, when it is too low, the operating current consumption will increase. r pu maximum resistance the maximum resistance must be set in such a way that the bus potential, which is determined by the sum total (i l ) of the input leaks of the devices connected to the sda bus and by r pu , can completely satisfy the input high level (v ih min) of the microcontroller and eeprom. however, a resistance value that satisfies sda rise time t r and fall time t f must be set. r pu maximum value = (v dd - v ih )/i l example: when v dd =3.0v and i l = 2 a r pu maximum value = (3.0v ? 3.0v 0.8)/2 a = 300k r pu minimum value a resistance corresponding to the low-level output voltage (v ol max) of sanyo?s eeprom must be set. r pu minimum value = (v dd ? v ol )/i ol example: when v dd =3.0v, v ol = 0.4v and i ol = 1ma r pu minimum value = (3.0v ? 0.4)/1ma = 2.6k recommended r pu setting r pu is set to strike a good balance between the operating frequency requirements and power consumption. if it is assumed that the sda load capacitance is 50pf and the sda output data strobe time is 500ns, r pu will be about r pu = 500ns/50pf = 10k . scl sda 1 2 89 dummy clock 9 start condition start condition sda r pu c bus i l eeprom i l master device
LE24CBK23MC no.a2069-16/21 3) precautions when turning on the power this product contains a power-on reset circuit for prev enting the inadvertent writing of data when the power is turned on. the following conditions must be met in order to ensure stable operation of this circuit. no data guarantees are given in the event of an instantaneous power failure during the internal write operation. item symbol v dd =2.5 to 5.5v unit min typ max power rise time t rise 100 ms power off time t off 10 ms power bottom voltage v bot 0.2 v notes: 1) the sda pin must be set to high and the scl pin to low or high. 2) steps must be taken to ensure that the sda and scl pins are not placed in a high-impedance state. a. if it is not possible to satisfy the instruction 1 in note above, and sda is set to low during power rise after the power has stabilized, the scl and sda pins must be controlled as shown below, with both pins set to high. b. if it is not possible to satisfy the instruction 2 in note above after the power has stabilized, software reset must be executed. c. if it is not possible to satisfy the instructions both 1 and 2 in note above after the power has stabilized, the steps in a must be executed, then software reset must be executed. 4) noise filter for the scl and sda pins this product contains a filter circuit for eliminating noise at the scl and sda pins. pulses of 100ns or less are not recognized because of this function. 5) function to inhibit writing when supply voltage is low this product contains a supply voltage monitoring circu it that inhibits inadvertent writing below the guaranteed operating supply voltage range. the data is protected by ensuring that write operations are not started at voltages (typ.) of 1.3v and below. 6) slave address setting this product does not have a slave address pin, but holds the slave address s0, s1 and s2 information internally. at the default, the slave address of this product is set to s0 = 0, s1 = 0, s2 = 0. during device addressing, execute this slave address following the device code. v dd 0v t off t rise v bot t low t dh t su.dat v dd scl sda t su.dat v dd scl sda
LE24CBK23MC no.a2069-17/21 7) precautions when wr ite protects operation. write to all memory areas is prohibited when the wp# pin of this product is set to the low level. the wp# pin must be held at the low level during the entire period from the start condition to the stop condition, and the following conditions must also be observed in order to ensure reliable write protect functions. parameter symbol v dd =2.5v to 5.5v unit min typ max wp# set-up time t su.wp 600 - - ns wp# hold time t hd.wp 600 - - ns 8) precautions when changing the mode these products selects bank mode operation or combine mode operation according to the cobm# pin status. changing the cobm# pin status while this product is active (during access to bank1 or bank2, including during the write period) is prohibited. the following cond itions must be observed in order to en sure reliable access functions in each mode. parameter symbol v dd =2.5v to 5.5v unit min typ max cobm# set-up time t su.cobm 10 - - s cobm# hold time t hd.cobm 5-- ms scl sda t su.wp t hd.wp wp# start condition stop condition scl1 or scl2 t su.cobm t hd.cobm cobm# sdl1 or sdl2 start condition stop condition
LE24CBK23MC no.a2069-18/21 9) writing with a rom writer from the combine mode this product enables two-bank configuration (2k bits + 2k bits) to be used as a pseudo-one-bank configuration (4k bits) by accessing the memory areas from the control port (sclc, sdac). as a result, data can be written using a rom writer with the eeprom serving as a regular 4k-bit eep rom. fix the port 1 and port 2 pins to high or low. the pin 3 (slave pin: s2) function of a regular 4k-bit eeprom product is assigned to the cobm# pin of the LE24CBK23MC. combine mode is entered by setting the cobm# pin to the low level. in combine mode, the scl2 and sda2 pins are don?t care (high level or low level or open). rom writer connection example in combine mode, the slave address (sa2 , sa1) is don?t care, and any combination can be entered (sa2 = 1, sa1 = 1 or sa2 = 1, sa1 = 0 or sa2 = 0, sa1 = 1 or sa2 = 0, sa1 = 0). memory area (4k-bit) the msb address in combined mode is a8. a8 is used to select the bank1 or bank2 area. set a8 = 0 to control the bank1 area, or a8 = 1 to control the bank2 area. 1 2 3 4 5 6 7 8 scl2 sda2 cobm# gnd v dd wp# scl1 sda1 LE24CBK23MC 1 2 3 4 5 6 7 8 s0 s1 s2 gnd v dd wp scl sda le24c04x (standard 4k-bit eeprom) 1 2 3 4 5 6 7 8 scl2 sda2 cobm# gnd v dd wp# scl1 sda1 LE24CBK23MC (don? care) connect to gnd level 1 0 0 1 sa2 sa1 r/w msb lsb combine mode (from scl1/sda1) a8 device code slave address device address word bank1 (2k-bit) bank2 (2k-bit) 000h 0ffh 100h 1ffh a8=0 a8=1
LE24CBK23MC no.a2069-19/21 10) system configuration image (hdmi system) this product can support two hdmi po rts simultaneously. both ports can be accessed at the same time when performing read operations of the ports. all the data can be written together from a image processor into the areas allocated to the two ports from the control port in a single operation. lcd-tv i 2 c LE24CBK23MC port 1 port 2 tmds tmds ddc ddc level shifter level shifter i 2 c hdmi connector hdmi receiver image processor hdmi connector
LE24CBK23MC no.a2069-20/21 11) peripheral circuit diagram example of connection with hdmi receiver *1: system power supply (3v) for hdmi receiver, etc. *2: reverse-current preventing diode this device can be operated by supplying power from any of the connected hdmi connectors (ddc + 5v) or the system power supply (3v). however, the supply voltage must be set so that the voltage stepped-down by the reverse-current preventing diode is within the gu aranteed operation voltage range of this device. *3: level shifter when connecting the 5v hdmi connector side with a 3v syst em, level shifters must generally be inserted. however, this is not necessary when the hdmi receiver supports 5v input signals. *4: write protection in general, use with hdmi applications assumes that this device is used as read-only after mounting. the write protection function is enabled to prevent write due to mi staken access, by setting the wp# pin to the ground level. when reconfiguration is required, write operation is enabled by connecting the wp# pin to the logic high level using a jumper, etc. *5: pull-up resistors for the i 2 c and ddc interfaces. see item 2) in the application notes for the resistance value settings. ddc+5v ddc_clk ddc_dat gnd ddc+5v ddc_clk ddc_dat gnd 6:scl1 LE24CBK23MC 5:sda1 1:scl2 2:sda2 4:gnd 7:wp# 3:cobm# 8:v dd scl1(3v) sda1(3v) scl2(3v) sda2(3v) *3 hdmi receiver v dd (3v) *5 r pu v dd (3v)*1 *2 *2 *2 *5 r pu *5 r pu *4 level shifter *3 level shifter hdmi connector hdmi connector
LE24CBK23MC no.a2069-21/21 ps this catalog provides information as of jun, 2012. specifications and information herein are subject to change without notice. sanyo semiconductor co.,ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. regarding monolithic semiconductors, if you should intend to use this ic continuously under high temperature, high current, high voltage, or drastic temperature change, even if it is used within the range of absolute maximum ratings or operating conditions, there is a possibility of decrease reliability. please contact us for a confirmation. sanyo semiconductor co.,ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. it is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equ ipment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above.

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